The present invention relates generally to integrated circuits having complementary metal oxide field effect transistors (CMOS) and more specifically to an improved radiation hard integrated circuit including CMOS devices.
The formation of VMOS transistors, vertical MOS transistors, to minimize the effect or limitations of lithography on forming the channel length is illustrated by, for example, Schroeder U.S. Pat. No. 4,296,429. More recently, the vertical CMOS technology forms an MOS transistor on a silicon trench side wall. The trench side wall is oxidized to form the gate oxide and the remaining trench void is filled with doped polycrystalline which creates the MOSFET gate electrode. The vertical MOS concept is currently used to make NMOS or PMOS transistors in Japanese DRAMs. Placing the MOS structure in the vertical position satisfactorily reduces the active area required for the device. Therefore, vertical MOSFETs have significantly higher packing density over their standard counterpart.
However, state of the art vertical MOSFETs have a very limited application due to the bulk substrate used to fabricate them. While the bulk substrate acts as a common source or drain for all transistors, stacked transistor are impossible and only one type of MOS transistor can be fabricated on a wafer. Therefore, vertical transistors must be either NMOS or PMOS on bulk substrates. Typical examples of this are described in articles: "A Trench MOSFET With Surface Source/Drain Contacts", Nakajima et al., IEDM '85, pp. 200-203; and, "Trench Transistor Cell With Self-Aligned Contact (TSAC) for Megabyte MOS DRAM", Yanagisawa et al., IEDM '86, pp. 132-135.
The investigation of parasitic vertical MOS transistors resulting from trench isolated lateral CMOS processes is described in Abstract No. 274, "Characterization of the Lateral and Vertical Parasitic Transistors in a Trench Isolated CMOS Process", M. C. Roberts et al., Eletrochemical Society Meeting, pp. 411-412. This articles indicates that the parasitic vertical MOS transistors will either not operate because of the voltages of the circuit or can be minimized by appropriate well doping and side wall oxide thickness.
Thus there exists a need to provide an integrated circuit which takes advantage of the vertical MOS transistors using the trench technology while maintaining the individual isolation of the isolated CMOS integrated devices.
Thus, it is an object of the present invention to provide an integrated circuit having high density and high speed digital integrated circuits.
Another object of the present invention is to provide a high density integrated circuit having both N and P channel devices on the same wafer with full dielectric isolation between individual devices.
An even further object of the present invention is to provide a method of fabricating submicron channel lengths.
A still further object of the present invention is to provide a method for fabricating complementary field effect transistors having low power mode of operation.
An even further object of the present invention is to provide a high density integrated circuit having complementary field effect transistors which are radiation hardened.
An even further object of the present invention is to provide a process which is capable of forming complementary field effect transistors as well as bipolar complementary transistors with suitable operating characteristics for digital integrated circuit applications.
These and other objects are achieved by using dielectrically isolated trenches with gate material therein to form a plurality of dielectrically isolated islands on a silicon-on-insulator (SOI) wafer. The buried oxide insulator offers the bottom dielectric isolation while the trenches offer the side wall isolation and side wall gates. The source, channel and drain regions are vertically aligned at the side walls of the trenches. Complementary MOS devices in adjacent islands may include a common gate material in the dielectric trenches which divide them. A buried high concentration impurity region reduces the parasitic resistance of the lower source or drain region at the bottom of the structure adjacent the base insulating layer. The lightly doped well creates a built-in lightly doped drain (LDD) structure. Diffused body and top source/drain regions for both N and P channel devices assure that the channel length is independent of the epitaxial thickness and the polysilicon gate width. This allows the device to be fabricated with very short lengths (i.e., submicron) without employing special lithographic tools. Submicron gate lengths will significantly increase speed.
A second gate segment isolated from the first gate segment along either a common or different vertical edge of an island using the same source drain and channel regions will form two insulated gate field effect transistors having their source and drain regions connected in parallel with separate gates. An island having a common channel separating a common source and drain with a separate and distinct second pair of sources and drains and a pair of gates across the channel regions between the buried source and the top drain and between the buried drain and the top source produce two field effect transistors having their source/drain paths in series with separate gates. Both these structures can be interconnected to produce appropriate logic circuits, for example a NAND gate. The separate surface source and drains may be along a common vertical edge or different vertical edges. For a more symmetrical device, the top source or drain region may be separated from the vertical edge by a lower impurity concentration region to produce a lightly doped drain (LDD).
A process for fabricating the unique integrated circuit having the vertical MOS transistor includes selectively forming a plurality of spaced first and second conductivity type buried regions in a first layer of a semiconductor material which is separated from a substrate by a base dielectric layer. A second layer of semiconductor material of the first conductivity type is formed on the first layer. Impurities of the second conductivity type are selectively introduced into regions of the second layer juxtaposed the second conductivity type buried regions to form a plurality of first regions of a first conductivity type and second regions of second conductivity type in the second layer. This forms the low impurity wells which form the source/drain regions.
First and second conductivity type impurities are selectively introduced into the second and first regions respectively to form third and fourth regions which are the channel regions. First and second conductivity type impurities are selectively introduced into the fourth and third regions respectively to form fifth and sixth regions respectively which are the surface source/drain regions.
Vertical trenches are then formed into the first and second layer down to the base dielectric layer to form a plurality of islands. The trenches ar filled with dielectric and gate materials to form isolated gate segments isolated from each other by dielectric isolation and from the vertical MOS transistors by gate insulation. On the non-MOS vertical MOS vertical edges, the gate segments are isolated by thicker field dielectric insulation.
The trenches may be formed before or after the selective impurity introduction to form the source and channel regions. The second layer is formed by low temperature epitaxy so as to substantially prevent an outdiffusion of the buried layers. The trenches may be formed by reactive ion etching.
The trenches may be totally filled with dielectric insulation which is selectively removed to form recesses in which the gate segments are to be formed. A portion of the trench oxide could be left at the base region of the trench becoming a pedestal oxide to the gate material. Gate material is then inserted to fill the recesses. Where gates are to be formed, the lateral edge of the second layer is exposed by removing the dielectric insulation and a gate insulation is formed on the vertical edge before filling with the gate material. If a gate is not to be formed on the opposed side, the opposed vertical edge is not exposed.
As an alternative, if the very low temperature EPI growth (plasma enhanced EPI growth) is used then the oxide at the base of the trench is not needed. Therefore, the trenches may also have gate insulation formed along the vertical edges of the first and second layer and filled with the gate material. The gate material is then selectively removed to form the gate segments separated by recesses and these recesses are filled with dielectric insulation. On the edges where gates are not to be formed, gate material is selectively removed along these vertical edges and are subsequently filled with dielectric insulation to form a field insulation along the previously exposed vertical edges and gate isolation on the opposed vertical edge.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.